1. Field of the Invention
The present invention relates to integrated circuit packaging technology, and more particularly to wafer-level ball grid array packages.
2. Background Art
Integrated circuit (IC) chips or dies are typically interfaced with other circuits using a package that can be attached to a printed circuit board (PCB). One such type of IC die package is a ball grid array (BGA) package. BGA packages provide for smaller footprints than many other package solutions available today. A BGA package has an array of solder ball pads located on a bottom external surface of a package substrate. Solder balls are attached to the solder ball pads. The solder balls are reflowed to attach the package to the PCB.
An advanced type of BGA package is a wafer-level BGA package. Wafer-level BGA packages have several names in industry, including wafer level chip scale packages (WLCSP), among others. In a wafer-level BGA package, the solder balls are mounted directly to the IC chip when the IC chip has not yet been singulated from its fabrication wafer. Wafer-level BGA packages can therefore be made very small, with high pin out, relative to other IC package types including traditional BGA packages.
A current move to tighter fabrication process technologies, such as 65 nm, with a continuing need to meet strict customer reliability requirements and ongoing cost pressures, is causing difficulties in implementing wafer-level BGA package technology. For example, due to the small size of the die used in wafer-level BGA packages, in some cases there is not enough space to accommodate all of the package pins at the pin pitch required for the end-use application
Thus, what is needed are improved wafer-level packaging fabrication techniques that can provide BGA packages at smaller package sizes, while enabling all the necessary package signals to be made available outside of the package at a pin pitch suitable for end-use applications.